The present invention relates to a process for production of a semiconductor device having the multi-layer wiring of dual damascene structure in the interlayer insulating film having a low dielectric constant. More particularly, the present invention relates to a process for production of a semiconductor device of dual damascene structure in good shape.
The recent advance in miniaturized and highly integrated semiconductor devices pose a serious problem with delay of electric signals resulting from the time constant of wiring. One way to address this problem is to form the conductive layer for the multi-layer wiring from low-resistant copper (Cu) in place of aluminum (Al) alloy.
Unfortunately, copper presents difficulties in patterning by dry etching unlike the conventional metallic material (such as aluminum) used for multi-layer wiring. Therefore, the multi-layer wiring of copper is formed usually by the damascene process, which consists of making a wiring groove in the insulating film and then burying copper in the wiring groove, thereby forming the wiring pattern. An example of the damascene process is disclosed in Japanese Patent Application No. Hei 10-143914. This process consists of forming a connecting hole and a wiring groove and then burying copper in the connecting hole and the wiring groove at the same time. This process is attracting attention because of its ability to decrease the number of steps.
Highly integrated semiconductor devices decrease in working speed as the wiring capacity increases. Consequently, they imperatively need the fine multi-layer wiring in which the interlayer insulating film is made of a low dielectric constant material which keeps low the wiring capacity.
The material for the low dielectric constant interlayer insulating film is fluorine-containing silicon oxide (FSG) having dielectric constant of about 3.5, which has been proved in practical use. It also includes ether polymers, such as polyaryl ether (PAE), and inorganic materials, such as hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ), which have a dielectric constant of about 2.7. Recently, attempts are being made to reduce the dielectric constant to about 2.2 by making the above-mentioned material porous.
If the dual damascene process is to be applied to the low dielectric constant interlayer insulating film, it is necessary to eliminate the technical limitations mentioned in the following.
First, the low dielectric constant film is liable to damage in the step of removing the resist, because it is similar in composition to the resist used for patterning. In other words, it is essential to protect the low dielectric constant film from damage when the resist is peeled off after etching through it or when the resist undergoes restoration treatment (which is performed when the resist pattern does not meet the product specification after processing).
Second, the process should be applicable to the borderless structure which does not allow alignment margin for the wiring and the connecting hole.
Semiconductor devices of the latest generation, in which the multi-layer wiring has a design rule of 0.18 μm, should be fabricated by the process applicable to the borderless structure. Therefore, it is important that the process be able to make the wiring groove and the connecting hole simultaneously in the interlayer insulating film including the low dielectric constant film by the dual damascene process without noticeable variation in via resistance due to incomplete alignment.
Third, for the wiring groove to be formed under good control, it is desirable that an etch preventing film be placed near the bottom of the wiring groove. However, an etch preventing film having a comparatively high dielectric constant, which is placed in the interlayer insulating film, increases the interlayer capacity.
Thus, there is a need for the dual damascene process for the interlayer structure of low dielectric constant film which is capable of forming the wiring groove under good control while keeping the capacity low.
The dual damascene process that eliminates the technical restrictions mentioned above is disclosed in Japanese Patent Laid-open Nos. 2000-150519 and 2001-44189.
The application of the dual damascene process (disclosed in Japanese Patent Laid-open No. 2001-44189) to the low dielectric constant interlayer film will be described below with reference to FIGS. 7 to 9, which are sectional views illustrating the conventional steps for forming the dual damascene structure.
The process starts with the first step shown in FIG. 7A. A substrate (not shown) is coated with an underlying insulating film 1 by deposition. On the underlying insulating film 1 is formed an interlayer insulating film which is composed of an organic film 2 and a silicon oxide (SiO2) film 3. In the interlayer insulating film is formed a buried wiring 4 of copper (Cu) film.
On the Cu buried wiring 4 is formed a silicon carbide (SiC) film 5 as an oxidation protecting layer. On the SiC film 5 are formed a carbon-containing silicon oxide (SiOC) film 6 as a methyl silsesquioxane (MSQ) film and a polyaryl ether (PAE) film 7 as an organic film.
Then, a silicon oxide (SiO2) film 8 as a first mask forming layer and a silicon nitride (SiN) film 9 as a second mask forming layer are formed sequentially. On the SiN film 9 is formed a resist mask 10 having a wiring groove pattern.
Then, as shown in FIG. 7B, dry etching is performed on the SiN film 9 through the resist mask 10, thereby forming a second mask 11 of SiN film having the wiring groove pattern. Subsequently, the resist mask 10 is removed.
A resist mask 12 having the connecting hole pattern is formed on the second mask 11 and the SiO2 film 8 in such a way that at least part of the resist having the connecting hole pattern overlaps with the second mask 11 of SiN film which has the wiring groove pattern.
As shown in FIG. 8A, dry etching is performed on the second mask 11 of SiN film and the SiO2 film 8 of the first mask forming layer through the resist mask 12 having the connecting hole pattern, thereby making a hole. Etching is performed on the PAE film 7, thereby making the connecting hole 13 which causes the SiOC film 6 to expose itself. The resist mask 12 is removed when the PAE film 7 undergoes etching.
While a hole is being made in the PAE film 7, the resist mask 12 gets thin, but it is possible to make the connecting hole 13 with a good opening shape because the first mask 8A of SiO2 film 8 still exists.
Then, as shown in FIG. 8B, etching is further performed on the SiOC film 6 until the connecting hole 13 reaches the SiC film 5, thereby making the connecting hole 14. When the connecting hole 14 is made, the SiO2 film 8 (which remains in the wiring groove forming region and forms the first mask 8A) is removed by etching through the second mask 11 of SiN film having the wiring groove pattern. This step makes the opening 15.
As shown in FIG. 8C, etching is performed on the PAE film 7 remaining at the bottom of the opening 15, thereby making the wiring groove 16. Etching is performed on the SiC film 5 at the bottom of the connecting hole 14, thereby causing the connecting hole 14 to communicate with the Cu buried wiring 4. In this way the desired dual damascene process is completed, or the process to make the wiring groove 16 and the connecting hole 14 is completed.
Incidentally, the second mask 11 of SiN film remaining outside the wiring groove forming region is removed while etching is being performed on the SiC film 5 at the bottom of the connecting hole 14.
Post-treatment with a chemical solution and RF sputtering are performed to remove etching residues remaining on the side wall of the wiring groove 16 and the connecting hole 14 and to restore the deteriorated Cu layer at the bottom of the connecting hole 14. Then, as shown in FIG. 9A, a Ta film 17 (as a barrier metal layer) is formed by sputtering. A Cu film 18 is deposited by electrolytic plating or sputtering, so that the wiring groove 16 and the connecting hole 14 are filled with a conducting film.
Then, as shown in FIG. 9B, the Ta film 17 and Cu film 18 deposited as mentioned above undergo chemical-mechanical polishing (CMP) to remove those parts unnecessary for wiring pattern. In this way there is obtained the multi-layer wiring of dual damascene structure.
Further, an SiC film 19 (as an oxidation protecting layer) is formed on the Cu film 18 as in the case of the underlying Cu buried wiring 4.
The dual damascene process with the double layer etching masks as mentioned above is exempt from the technical limitations mentioned above when applied to the low dielectric constant interlayer film structure.
In other words, it is possible to recover the resist masks 10 and 12 not meeting the product specification by treatment on the SiO2 8 film as the first mask forming layer or on the SiN film 9 as the second mask forming layer. Moreover, it is also possible to remove the resist mask 12 (used to make the connecting hole) when the connecting hole 13 is made by etching on the PAE film 7. Therefore, it is possible to peel off the resist without damage to the low dielectric constant film.
Since the connecting hole 13 (or the connecting hole 14) is made through the second mask 11 of SiN film having the wiring groove pattern, there is no possibility that the connecting hole 14 varies in dimensions even when incomplete alignment occurs between the wiring groove 16 and the connecting hole 14.
When the wiring groove 16 is made in the PAE film 7 formed on the SiOC film 6, the combination of the inorganic MSQ film (SiOC film 6) and the organic polymer film (PAE film 7) easily allows an adequate etching selectivity. This makes it possible to control the depth of the wiring groove 16 easily without the help of the etching preventing film (such as SiN film) having a high dielectric constant.
The dual damascene process mentioned above has still problems as follows when it is applied to the multi-layer wiring that should conform to the design rule of 0.18 μm.
First, the second mask forming layer (or the SiN film 9) becomes thicker than necessary. The second mask 11 is intended for etching on the SiOC film (MSQ film) 6 as the interlayer film for the connecting hole, thereby making the connecting hole 14 and also making the opening 15 in the wiring groove forming region. Therefore, it needs a certain thickness. For example, in the case where the SiOC film 6, 400 nm thick, as the interlayer film for the connecting hole, is to be made by using the SiN film 9 as the second mask 11, the SiN film 9 should have a thickness of 100 to 150 nm from the view point of etching selectivity, so as to prevent the wiring groove from opening expansion or shoulder rounding.
Second, the resist mask 12 is formed on the step several times. This presents difficulties in forming fine patterns accurately.
In the step of fabricating the SiN film 9 (as the second mask forming layer), thereby forming the second mask 11 having the wiring groove pattern, the etching selectivity (SiN/SiO2) for the SiO2 film 8 as the first mask forming layer is only about 2 to 3. Therefore, in case of over etching on the SiN film 9, the underlying SiO2 film 8 is attacked more than 30 nm, as shown in FIG. 7B. This necessitates forming the resist mask 12 (having the connecting hole pattern) on the step with a height of 130 to 180 nm.
However, forming a fine resist pattern for the design rule of 0.10 μm on a local step slightly lower than 200 nm is much more difficult than forming it on a flat surface on account of resist mask spreading and uncontrollable line width.
Third, in the case where the common antireflection film (BARC) of coating type is used in the lithography step, it varies in its buried shape depending on the dimensions and density of the pattern on the second mask 11. This results in variation in depth of field, which in turn deteriorates the shape of the resist at the time of exposure or deteriorates the shape of the second mask 11 when the connecting hole is made by etching on the BARC film.
Fourth, according to the conventional dual damascene process mentioned above, patterning of the wiring groove through the resist mask 10 is performed before patterning of the connecting hole 13 through the resist mask 12. This leads to indirect mask alignment for the wiring groove 16 and the connecting hole 14. As compared with the ordinary process in which the pattern of the connecting hole is made first, the above-mentioned process causes more incomplete alignment for the upper wiring and the connecting hole.
A solution to the above-mentioned problems is disclosed in Japanese Patent Laid-open No. 2000-150519, for example. According to this disclosure, the second mask is formed from a metal so as to increase the etching selectivity for the MSQ film (as the connecting hole interlayer), thereby reducing the thickness of the second mask and decreasing the step arising from resist patterning.
Unfortunately, the metal film is almost opaque to light (with a wavelength of 200 to 1000 nm) used for mask alignment. Therefore, if the metal film is formed over the entire surface, it makes it impossible to perform alignment with light of ordinary wave lengths or alignment by image processing in the exposure step.
Thus, it is an object of the present invention to provide a process for producing in high yields a highly reliable and high-performance semiconductor device having a multi-layer wiring structure. The process is characterized in that a load on resist patterning is reduced and a good shape is obtained by the dual damascene process when the dual damascene structure is formed in the low dielectric constant interlayer insulating film of PAE film and MSQ film.